参数资料
型号: V826632K24S
厂商: Mosel Vitelic, Corp.
英文描述: 2.5 VOLT 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE
中文描述: 2.5伏32M的高性能× 64 DDR SDRAM内存模块缓冲
文件页数: 11/14页
文件大小: 126K
代理商: V826632K24S
6
V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
29
Minimum RAS to CAS delay(=tRCD)
20ns
50h
30
Minimum active to precharge time(=tRAS)
50ns
45ns
32h
2Dh
31
Module ROW density
256MB
40h
32
Command and address signal input setup time
1.1ns
0.9ns
B0h
90h
33
Command and address signal input hold time
1.1ns
0.9ns
B0h
90h
34
Data signal input setup time
0.6ns
0.5ns
60h
50h
35
Data signal input hold time
0.6ns
0.5ns
60h
50h
36-40
Superset information (may be used in future)
00h
41
SDRAM device minimum active to active/auto-refresh time
(=tRC)
70ns
65ns
46h
41h
42
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=tRFC)
80ns
75ns
50h
4Bh
43
SDRAM device maximum device cycle time (=tCK MAX)
12ns
30h
44
SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
0.6ns
0.5ns
3Ch
32h
45
SDRAM device maximum read datahold skew factor (=tQHS)
1ns
0.75ns
A0h
75h
46-61
Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release
00h
63
Checksum for Bytes 0 ~ 62
-
E7h
22h
F2h
64
Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71
....... Manufacturer JEDEC ID code
Mosel Vitelic
40h
72
Manufacturing location
01h
73-90
Module part number (ASCII)
V826632K24S
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Week)
-
94
Manufacturing date (Year)
-
95~98
Assembly serial #
-
99~127
Manufacturer specific data (may be used in future)
Undefined
00h
128~255 Open for customer use
Undefined
00h
Byte #
Function described
Function Supported
Hex value
A1
B0
B1
A1
B0
B1
Serial Presence Detect Information (cont.)
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