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参数资料
| 型号： | V827332U04S |
| 厂商： | Mosel Vitelic, Corp. |
| 英文描述： | 2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE |
| 中文描述： | 2.5伏32M × 72配置高性能寄存ECC DDR SDRAM内存模块 |
| 文件页数： | 14/14页 |
| 文件大小： | 294K |
| 代理商： | V827332U04S |
MOSEL VITELIC
V827332U04S
9
V827332U04S Rev. 1.2 March 2002
DDR SDRAM IDD SPEC TABLE
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
A1(PC1600@CL=2)
B0(PC2100B@CL=2.5)
B1(PC2100A@CL=2)
Unit
Typical
Worst
Typical
Worst
Typical
Worst
IDD0
1450
1440
1350
1440
1080
1170
mA
IDD1
1650
1710
1575
1710
1280
1395
mA
IDD2P
750
720
675
720
540
585
mA
IDD2F
895
945
655
945
720
765
mA
IDD2Q
830
810
765
810
630
675
mA
IDD3P
980
765
720
765
585
630
mA
IDD3N
900
990
900
990
720
810
mA
IDD4R
1980
2250
1980
2250
1620
1845
mA
IDD4W
2115
2385
2115
2385
1710
1890
mA
IDD5
2115
2385
2115
2385
1710
1890
mA
IDD6
Normal
36
mA
Low power
18
mA
IDD7
3375
3825
3375
3825
2745
3150
mA
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