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参数资料
| 型号： | V827464K24SATGD3 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.65 ns, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 14/14页 |
| 文件大小： | 206K |
| 代理商： | V827464K24SATGD3 |
ProMOS TECHNOLOGIES
V827464K24SA
9
V827464K24SA Rev.1.2 April 2006
DDR SDRAM IDD SPEC TABLE
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR333 (166MHz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR400B (200MHz, CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK, tRC=12*tCK, tRAS=8*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR400A (200MHz, CL=2.5) : tCK=5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=12*tCK, tRAS=8*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
D0 / D3
PC3200A@CL=3
C0
PC2100A@CL=2.5
B1
PC2100A@CL=2
B0
PC2100B@CL=2.5
Unit
IDD0
1080
1060
870
mA
IDD1
1440
1280
1100
mA
IDD2P
120
mA
IDD2F
620
560
500
mA
IDD2Q
420
380
340
mA
IDD3P
450
370
290
mA
IDD3N
810
550
460
mA
IDD4R
2430
1700
1400
mA
IDD4W
2250
1600
1350
mA
IDD5
1890
1800
1700
mA
IDD6
Normal
54
mA
Low power
33
mA
IDD7
3600
3180
2580
mA
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