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参数资料
| 型号： | V827464K24SATGD3 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.65 ns, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 2/14页 |
| 文件大小： | 206K |
| 代理商： | V827464K24SATGD3 |
10
ProMOS TECHNOLOGIES
V827464K24SA
V827464K24SA Rev. 1.2 April 2006
AC Characteristics (AC operating conditions unless otherwise noted)
Parameter
Sym-
bol
(DDR400A)
D0
(DDR400B)
D3
(DDR333)
C0
(DDR266A)
B1
(DDR266B)
B0
Unit Note
Min
Max Min
Max
Row Cycle Time
tRC
60
-
60
-
60
-
65
-
65
-
ns
Auto Refresh Row Cycle Time
tRFC
70
-
70
-
72
-
75
-
75
-
ns
Row Active Time
tRAS
40
120K
40
120K
42
120K
45
120K
45
120K
ns
Row Address to Column Address De-
lay
tRCD
15
-
15
-
18
-
15
-
20
-
ns
Row Active to Row Active Delay
tRRD
10
-
10
-
12
-
15
-
15
-
ns
Column Address to Column Address
Delay
tCCD
1
-
1
-
1
-
1
-
1
-
CLK
Row Precharge Time
tRP
15
-
15
-
18
-
15
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
12
-
15
-
15
-
ns
Last Data-In to Read Command
tDRL
1
-
1
-
1
-
1
-
1
-
CLK
Auto Precharge Write Recovery + Pre-
charge Time
tDAL
35
-
35
-
35
-
35
-
35
-
ns
System Clock
Cycle Time
CAS Latency = 3
tCK
5
12
5
12
-
12
-
12
-
12
ns
CAS Latency = 2.5
5
12
6
12
6
12
7
12
7.5
12
ns
CAS Latency = 2
7.5
12
7.5
12
7.5
12
7.5
12
10
12
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CLK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CLK
Data-Out edge to Clock edge Skew
tAC
-0.65
0.65
-0.65
0.65
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DQS-Out edge to Clock edge Skew
tDQSCK -0.60 0.60 -0.60 0.60 -0.75 0.75 -0.75 0.75 -0.75 0.75
ns
DQS-Out edge to Data-Out edge Skew tDQSQ
-
0.40
-
0.40
-
0.45
-
0.5
-
0.5
ns
Data-Out hold time from DQS
tQH
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
- .75ns
-
tHPmin
- .75ns
-
ns
1
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns
1
Input Setup Time (fast slew rate)
tIS
0.6
-
0.6
-
0.75
-
0.9
-
0.9
-
ns
2,3,5,6
Input Hold Time (fast slew rate)
tIH
0.6
-
0.6
-
0.75
-
0.9
-
0.9
-
ns
2,3,5,6
Input Setup Time (slow slew rate)
tIS
0.75
-
0.75
-
0.8
-
1.0
-
1.0
-
ns
2,4,5,6
Input Hold Time (slow slew rate)
tIH
0.75
-
0.75
-
0.8
-
1.0
-
1.0
-
ns
2,4,5,6
Input Pulse Width
tIPW
0.4
0.6
0.4
0.6
0.4
0.6
2.2
-
2.2
-
ns
6
Write DQS High Level Width
tDQSH
0.35
CLK
Write DQS Low Level Width
tDQSL
0.35
CLK
CLK to First Rising edge of DQS-In
tDQSS
0.72
1.25
0.72
1.25
0.75
1.25
0.75
1.25
0.75
1.25
CLK
Data-In Setup Time to DQS-In (DQ &
DM)
tDS
0.40
-
0.40
-
0.45
-
0.5
-
0.5
-
ns
7
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