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参数资料
| 型号： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 14/20页 |
| 文件大小： | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 14 of 20
AC Electrical Characteristics
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5% (3.35
–
3.465V), f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
Pin Capacitance/Inductance
C
IN
Input Pin Capacitance
C
OUT
Output Pin Capacitance
L
IN
Input Pin Inductance
Serial Input Port
V
IL
Input Low Voltage
V
IH
Input High Voltage
I
IL
Input Low Current
I
IH
Input High Current
I
OL
Sink Current into SDATA or SCLOCK,
Open Drain N-Channel Device On
C
IN
Input Capacitance of SDATA and
SCLOCK
C
SDATA
Total Capacitance of SDATA Bus
C
SCLOCK
Total Capacitance of SCLOCK Bus
Except X1 and X2
5
6
7
pF
pF
nH
V
DDQ3
= 3.3V
V
DDQ3
= 3.3V
0.3V
DDQ3
V
V
μA
μA
mA
0.7V
DDQ3
10
10
I
OL
= 0.3(V
DDQ3
)
6
10
pF
400
400
pF
pF
3.3V DC Electrical Characteristics
(continued) T
A
= 0
°
C to +70
°
C, V
DDQ3
= V
DDQ2
= 3.3V±5% (3.135
–
3.465V)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
CPU AGP Clock Outputs, CPU0:3, AGP_F, AGP0 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequen-
cy stabilization.
Average value during switching transition. Used
for determining series termination value.
CPU = 66.6 MHz
Min.
Typ.
15
66.6
5.2
5
1
1
45
Unit
ns
MHz
ns
ns
V/ns
V/ns
%
ps
Max.
t
P
f
t
H
t
L
t
R
t
F
t
D
t
JC
Period
Frequency, Actual
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
4
4
55
250
t
SK
f
ST
Output Skew
Frequency Stabilization from
Power-up (cold start)
250
3
ps
ms
Z
o
AC Output Impedance
10
15
20
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