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参数资料
| 型号： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 7/20页 |
| 文件大小： | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 7 of 20
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the
“
reserved
”
bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7.
Table 7
gives the bit formats for registers located in Data
Bytes 0
–
6.
Table 8
details additional frequency selections that are avail-
able through the serial data interface.
Table 9
details the select functions for Byte 0, bits 1 and 0.
Table 7. Data Bytes 0
–
6 Serial Configuration Map
Affected Pin
Pin No.
Pin Name
Data Byte 0
7
--
6
--
5
--
4
--
3
8, 47, 48
FS0:2
Bit(s)
Control Function
Bit Control
Default
0
1
--
--
--
--
(Reserved)
SEL_2
SEL_1
SEL_0
BYT0 /FS#
--
--
0
0
0
0
0
Refer to
Table 8
Refer to
Table 8
Refer to
Table 8
Frequency Controlled
by external pins FS0:2
--
Function (See
Table 9
for function details)
Normal Operation
(Reserved)
Spread Spectrum On
All Outputs Three-stated
Frequency Controlled
by SEL_0:2, above
--
2
(Reserved)
Bit 1
0
0
1
1
0
00
1
–
0
--
--
Bit 0
0
1
0
1
Data Byte 1
7
6
5
4
3
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
--
--
--
--
40
41
43
44
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
--
--
--
--
--
--
0
0
0
0
1
1
1
1
CPU3
CPU2
CPU1
CPU0
Low
Low
Low
Low
Active
Active
Active
Active
--
8
--
14
13
12
11
9
--
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
0
1
0
1
1
1
1
1
PCI_F
--
PCI4
PCI3
PCI2
PCI1
PCI0
Low
--
Low
Low
Low
Low
Low
Active
--
Active
Active
Active
Active
Active
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