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参数资料
| 型号： | W134 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 5/12页 |
| 文件大小： | 188K |
| 代理商： | W134 |
W134M/W134S
5
Table 4
shows the logic for selecting the Bypass and Test
modes. The select bits, S0 and S1, control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the Refclk input all the way to the output, bypassing both
the PLL and the Phase Aligner. In the Output Test mode (OE),
both the Clk and ClkB outputs are put into a high-impedance
state (Hi-Z). This can be used for component testing and for
board-level testing.
Table 5
shows the logic for selecting the Power-down mode,
using the PwrDnB input signal. PwrDnB is active LOW (en-
abled when 0). When PwrDnB is disabled, the DRCG is in its
normal mode. When PwrDnB is enabled, the DRCG is put into
a powered-off state, and the Clk and ClkB outputs are three-
stated.
Table of Frequencies and Gear Ratios
Table 6
shows several supported Pclk and Busclk frequencies,
the corresponding A and B dividers required in the DRCG PLL,
and the corresponding M and N dividers in the gear ratio logic.
The column Ratio gives the Gear Ratio as defined Pclk/Synclk
(same as M and N). The column F@PD gives the divided down
frequency (in MHz) at the Phase Detector, where
F@PD=Pclk/M=Synclk/N.
State Transitions
The clock source has three fundamental operating states.
Fig-
ure 4
shows the state diagram with each transition labelled A
through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and
StopB.
In Power-down mode, the clock source is powered down with
the control signal, PwrDnB, equal to 0. The control signals S0
and S1 must be stable before power is applied to the device,
and can only be changed in Power-down mode (PwrDnB=0).
The reference inputs, V
DDR
and V
DDPD
, may remain on or may
be grounded during the Power-down mode.
Table 3. Clock Stop Mode Selection
Mode
Normal
StopB
1
Clk
PAclk
ClkB
PAclkB
Clk Stop
0
V
X,STOP
V
X,STOP
Table 4. Bypass and Test Mode Selection
Mode
S0
0
S1
0
Bypclk
(int.)
Gnd
Clk
PAclk
ClkB
PAclkB
Normal
Output Test (OE)
0
1
-
Hi-Z
Hi-Z
Bypass
1
0
PLLclk
PLLclk
PLLclkB
Test
1
1
Refclk
Refclk
RefclkB
Table 5. Power-down Mode Selection
Mode
PwrDnB
Clk
ClkB
Normal
1
PAclk
PAclkB
Power-down
0
GND
GND
Table 6. Examples of Frequencies, Dividers, and Gear Ratios
Pclk
67
Refclk
33
Busclk
267
Synclk
67
A
8
B
1
M
2
N
2
Ratio
1.0
F@PD
33
100
50
300
75
6
1
8
6
1.33
12.5
100
50
400
100
8
1
4
4
1.0
25
133
67
267
67
4
1
4
2
2.0
33
133
67
400
100
6
1
8
6
1.33
16.7
Test
M
N
L
K
Normal
Power-Down
Clk Stop
D
C
G
A
E
F
H
V
DD
Turn-On
V
DD
Turn-On
V
DD
Turn-On
V
DD
Turn-On
B
J
Figure 4. Clock Source State Diagram
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