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参数资料
| 型号： | W134 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 7/12页 |
| 文件大小： | 188K |
| 代理商： | W134 |
W134M/W134S
7
Figure 5
shows that the Clk Stop to Normal transition goes
through three phases. During t
CLKON
, the clock output is not
specified and can have glitches. For t
CLKON
< t< t
CLKSETL
, the
clock output is enabled and must be glitch-free. For
t>t
CLKSETL
, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At this
time, the clock output must also meet the voltage and timing
specifications of
Table 14
. The outputs are in a high-imped-
ance state during the Clk Stop mode.
Table 8. State Transition Latency Specifications
Transition
From
To
Transition Latency
Symbol
Description
Max.
A
Power-down
Normal
t
POWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding t
DISTLOCK
).
Time from PwrDnB until the internal PLL and
clock has turned ON and settled.
C
Power-down
Clk Stop
t
POWERUP
3 ms
K
Power-down
Test
t
POWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding t
DISTLOCK
).
Time from V
DD
is applied and settled until
Clk/ClkB output settled (excluding t
DISTLOCK
).
Time from V
DD
is applied and settled until
internal PLL and clock has turned ON and
settled.
G
V
DD
ON
Normal
t
POWERUP
3 ms
H
V
DD
ON
Clk Stop
t
POWERUP
3 ms
M
V
DD
ON
Test
t
POWERUP
3 ms
Time from V
DD
is applied and settled until
internal PLL and clock has turned ON and
settled.
J
Normal
Normal
t
MULT
1 ms
Time from when Mult0 or Mult1 changed until
Clk/ClkB output resettled (excluding
t
DISTLOCK
).
Time from StopB until Clk/ClkB provides
glitch-free clock edges.
E
Clk Stop
Normal
t
CLKON
10 ns
E
Clk Stop
Normal
t
CLKSETL
20 cycles
Time from StopB to Clk/ClkB output settled to
within 50 ps of the phase before CLK/CLKB
was disabled.
Time from StopB
Φ
to Clk/ClkB output
disabled.
F
Normal
Clk Stop
t
CLKOFF
5 ns
L
Test
Normal
t
CTL
3 ms
Time from when S0 or S1 is changed until
CLK/CLKB output has resettled (excluding
t
DISTLOCK
).
Time from when S0 or S1 is changed until
CLK/CLKB output has resettled (excluding
t
DISTLOCK
).
Time from PwrDnB
Φ
to the device in Power-
down.
N
Normal
Test
t
CTL
3 ms
B,D
Normal or Clk Stop
Power-down
t
POWERDN
1 ms
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