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| 型号： | W182G |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|CMOS|SOP|14PIN|PLASTIC |
| 中文描述： | 杂项时钟发生器|的CMOS |专科| 14PIN |塑料 |
| 文件页数： | 7/9页 |
| 文件大小： | 124K |
| 代理商： | W182G |
W182
Document #: 38-07151 Rev. **
Page 7 of 9
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in
Figure 4
should be used.
V
DD
decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-
μ
F decoupling capacitor should be
placed as close to the V
DD
pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-
μ
F decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
DD
connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5
shows a recommended a 2-layer board layout.
Figure 4. Recommended Circuit Configuration
GND
W
14
13
12
11
10
9
8
1
2
3
4
5
6
7
C1
0.1 μF
FB
C2
10 μF Tantalum
3.3V or 5V System Supply
Clock
Output
R1
Xtal Connection or NC
Xtal Connection or Reference Input
C3
0.1
μF
Clock Output
High-frequency supply decoupling
capacitor (0.1-μF recommended).
Common supply low frequency
decoupling capacitor (10-μF tantalum
recommended).
Match value to line impedance
FB
Ferrite Bead
C1, C3 =
C2 =
R1 =
=
R1
C1
C2
G
G
FB
= Via To GND Plane
G
NC
G
(3.3V or 5V)
C3
G
Power Supply Input
Xtal Connection or Reference Input
G
Xtal Connection or
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
W182
W182-5
Package
Name
G
Package Type
14-Pin Plastic SOIC (150-mil)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W182-HEA-100 | 制造商:NTE Electronics 功能描述: |
| W182-HEA-25 | 制造商:NTE Electronics 功能描述: |
| W182-HEA-50 | 制造商:NTE Electronics 功能描述: |
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| W183-5 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Full Feature Peak Reducing EMI Solution |
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