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参数资料
| 型号： | W204 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 6/16页 |
| 文件大小： | 177K |
| 代理商： | W204 |
W204
PRELIMINARY
Document #: 38-07264 Rev. *A
Page 6 of 16
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the
“
reserved
”
bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7.
Table 4
gives the bit formats for registers located in Data
Bytes 3
–
6.
Table 5
details additional frequency selections that are avail-
able through the serial data interface.
Table 6
details the select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 3
–
6 Serial Configuration Map
Affected Pin
Pin No.
Pin Name
Data Byte 3
7
--
6
--
5
--
4
--
3
--
Bit(s)
Control Function
Bit Control
Default
0
1
--
--
--
--
--
SEL_3
SEL_2
SEL_1
SEL_0
BYT3_FS#
Refer to
Table 5
Refer to
Table 5
Refer to
Table 5
Refer to
Table 5
0
0
0
0
0
Frequency Controlled
by external FS0:1 pins
--
Function (See
Table 6
for function details)
Spread Spectrum OFF
Test Mode
Spread Spectrum ON (default)
All Outputs Three-stated
Frequency Controlled
by BYT3 SEL_(3:0)
--
2
--
--
--
--
(Reserved)
Bit 1
0
0
1
1
0
10
1
–
0
Bit 0
0
1
0
1
Data Byte 4
7
6
5
4
3
2
1
0
Data Byte 5
7
6
5
4
3
2
1
0
Data Byte 6
7
6
5
4
3
2
1
0
--
23
--
--
35
36
39
40
--
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
0
1
0
0
1
1
1
1
24_48MHz
--
--
CPU3
CPU2
CPU1
CPU0
Low
--
--
Low
Low
Low
Low
Active
--
--
Active
Active
Active
Active
7
PCI_F
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
1
1
17
16
14
13
11
10
8
--
--
44
45
--
47
2
1
--
--
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
--
--
0
0
1
1
0
1
1
1
APIC1
APIC0
--
REF2
REF1
REF0
Low
Low
--
Low
Low
Low
Active
Active
--
Active
Active
Active
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