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参数资料
| 型号： | W204 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 9/16页 |
| 文件大小： | 177K |
| 代理商： | W204 |
W204
PRELIMINARY
Document #: 38-07264 Rev. *A
Page 9 of 16
Signaling Requirements
As shown in
Figure 6
, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a
“
start bit
”
as shown in
Figure
7
. A
“
stop bit
”
signifies that a transmission has ended.
As stated previously, the W204 sends an
“
acknowledge
”
pulse
after receiving eight data bits in each byte as shown in
Figure
8
.
Sending Data to the W204
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double buff-
ered). Partial transmission is allowed meaning that a transmis-
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Trans-
mission is truncated with either a stop bit or new start bit (re-
start condition).
Figure 6. Serial Data Bus Valid Data Bit
Figure 7. Serial Data Bus Start and Stop Bit
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
SDATA
SCLOCK
Start
Bit
Stop
Bit
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相关代理商/技术参数 |
参数描述 |
|---|---|
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| W2-04-LFR | 制造商:FRONTIER 制造商全称:Frontier Electronics. 功能描述:2A SILICON SINGLE-PHASE BRIDGE RECTIFIERS |
| W205 | 制造商:ATI 功能描述:MOUNTED POINT |
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