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参数资料
| 型号： | W210H |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC |
| 中文描述： | CPU系统时钟发生器|的CMOS | SSOP封装| 48PIN |塑料 |
| 文件页数： | 1/14页 |
| 文件大小： | 215K |
| 代理商： | W210H |
Spread Spectrum FTG for VIA K7 Chipset
W210
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
April 11, 2000, rev. *C
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
Single-chip system frequency synthesizer for VIA K7
chipset
One pair of differential CPU outputs for K7 Processor
One open-drain CPU output for VIA K7 chipset
Six copies of PCI output
One 48-MHz output for USB
One 24-MHz or 48-MHz output for SIO
Two buffered reference outputs
Thirteen SDRAM outputs provide support for 3 DIMMs
Supports frequencies up to 200 MHz
I
2
C interface for programming
Power management control inputs
Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
: .................................................................... 3.3V±5%
I
2
C is a trademark of Philips Corporation.
Table 1. Mode Input Table
Mode
0
1
Pin 2
CPU_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
CPU
(MHz)
133.3
75
100.2
66.8
79
110
115
120
133.3
83.3
100.2
66.8
124
129
138
143
PCI0:5
(MHz)
33.3
37.5
33.3
33.4
39.5
36.7
38.3
30
33.3
27.7
33.3
33.4
31.0
32.3
34.5
35.8
Spread
Spectrum
±0.5%
±0.5%
±0.5%
±0.5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Block Diagram
Pin Configuration
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
[1]
VDDQ3
REF0/(CPU_STOP#)
REF1/FS0
PCI0/MODE
PCI1/FS1
XTAL
OSC
PLL Ref Freq
PLL 1
X2
X1
VDDQ3
CStop
PCI2
PCI3
PCI4
48MHz/FS2
VDDQ3
PLL2
÷2,3,4
PWRDWN#
VDDQ3
PCI5
I
2
C
Logic
SCLK
I/O Pin
Control
SDRAM0:12
SDRAMIN
13
CPUT0
CPUC0
÷2
CPUT_CS
VDDQ3
REF0/(CPU_STOP#)
GND
X1
X2
VDDQ3
PCI0/MODE
PCI1/FS1*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
I
2
C
{
GND
SDATA
SCLK
W
REF1/FS0*
GND
CPUT_CS
GND
CPUC0
CPUT0
VDDQ3
PWRDWN#*
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS2*
24_48MHz/FS3^
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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