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参数资料
| 型号： | W210H |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC |
| 中文描述： | CPU系统时钟发生器|的CMOS | SSOP封装| 48PIN |塑料 |
| 文件页数： | 5/14页 |
| 文件大小： | 215K |
| 代理商： | W210H |
W210
5
Serial Data Interface
The W210 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W210 initializes with
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions.
Table 3
summarizes the control functions of
the serial data interface.
Operation
Data is written to the W210 in eleven bytes of eight bits each.
Bytes are written in the order shown in
Table 4
.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency tran-
sition allows CPU frequency change under
normal system operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts clock output into a high impedance state.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro-
duction device testing.
No user application. Register bit must be writ-
ten as 0.
Table 4. Byte Writing Sequence
Byte Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W210 to accept the bits in Data Bytes 0
–
6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W210 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Code
Don
’
t Care
Unused by the W210, therefore bit values are ignored (
“
Don
’
t Care
”
).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
3
Byte Count
Don
’
t Care
Unused by the W210, therefore bit values are ignored (
“
Don
’
t Care
”
).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
4
Data Byte 0
Refer to
Table 5
The data bits in Data Bytes 0
–
7 set internal W210 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to
Table 5
, Data Byte Serial Configuration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
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