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参数资料
| 型号： | W210H |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC |
| 中文描述： | CPU系统时钟发生器|的CMOS | SSOP封装| 48PIN |塑料 |
| 文件页数： | 12/14页 |
| 文件大小： | 215K |
| 代理商： | W210H |
W210
12
Document #: 38-00846-C
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
24.004
MHz
f
D
m/n
Deviation from 24 MHz
(24.004
–
24)/24
+167
ppm
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
t
R
t
F
t
D
f
ST
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Cl
p
ip
Clock Chip
CPU
Driver
1.5V
R1
68
Z0 = 52
T2
”
Z0 = 52
Length = 5
”
T1
R8
47
CPUCLK_T
T5
”
Z0 = 52
Length = 5
”
T4
R9
47
20p
20p
CPUCLK_C
1.5V
R3
68
Figure 5. K7 Open Drain Clock Driver Test Circuit
Ordering Information
Ordering Code
W210
Package
Name
H
Package Type
48-pin SSOP (300 mils)
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