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参数资料
| 型号： | W219 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 11/15页 |
| 文件大小： | 175K |
| 代理商： | W219 |
W219B
PRELIMINARY
Document #: 38-07220 Rev. *A
Page 11 of 15
AC Electrical Characteristics
[9]
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
f
XTL
= 14.31818 MHz
Notes:
11.
12. T
HIGH
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
13. T
is measured at 0.4V for all outputs.
14. The time specified is measured from when V
DDQ3
achieves its nominal operating level (typical condition V
DDQ3
= 3.3V) until the frequency output is stable and
operating within specification.
15. T
and T
FALL
are measured as a transition through the threshold region V
ol
= 0.4V and V
oh
= 2.0V (1 mA) JEDEC specification for 2.5V outputs, and V
ol
=
0.4V and V
oh
Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
Parameter
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
Description
66.6-MHz Host
Min.
15.0
5.2
5.0
0.4
0.4
100-MHz Host
Min.
10.0
3.0
2.8
0.4
0.4
133-MHz Host
Min.
7.5
1.87
1.67
0.4
0.4
Unit
ns
ns
ns
ns
ns
Notes
11
14
Max.
15.5
N/A
N/A
1.6
1.6
Max.
10.5
N/A
N/A
1.6
1.6
Max.
8.0
N/A
N/A
1.6
1.6
Host/CPUCLK Period
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
15
15
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
SDRAM CLK Period
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
1.6
ns
ns
ns
ns
ns
11
14
15
15
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
APIC CLK Period
APIC CLK High Time
APIC CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
60.0
25.5
25.3
0.4
0.4
64.0
N/A
N/A
1.6
1.6
60.0
25.5
25.30
0.4
0.4
N/A
N/A
N/A
1.6
1.6
60.0
25.5
25.30
0.4
0.4
64.0
N/A
N/A
1.6
1.6
ns
ns
ns
ns
ns
11
14
15
15
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
3V66 CLK Period
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
30.0
12.0
12.0
0.4
0.4
N/A
N/A
N/A
1.6
1.6
30.0
12.0
12.0
0.4
0.4
N/A
N/A
N/A
1.6
1.6
30.0
12.0
12.0
0.4
0.4
N/A
N/A
N/A
1.6
1.6
ns
ns
ns
ns
ns
11, 13
14
15
15
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
PCI CLK Period
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
15.0
5.25
5.05
0.5
0.5
16.0
N/A
N/A
2.0
2.0
15.0
5.25
5.05
0.5
0.5
16.0
N/A
N/A
2.0
2.0
15.0
5.25
5.05
0.5
0.5
16.0
N/A
N/A
2.0
2.0
ns
ns
ns
ns
ns
11, 12
14
15
15
tp
ZL
, tp
ZH
tp
LZ
, tp
ZH
Output Enable Delay (All outputs)
Output Disable Delay
(All outputs)
All Clock Stabilization from
Power-Up
30.0
12.0
N/A
N/A
30.0
12.0
N/A
N/A
30.0
12.0
N/A
N/A
ns
ns
15
t
stable
12.0
N/A
12.0
N/A
12.0
N/A
ms
15
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