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参数资料
| 型号： | W219 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 4/15页 |
| 文件大小： | 175K |
| 代理商： | W219 |
W219B
PRELIMINARY
Document #: 38-07220 Rev. *A
Page 4 of 15
Power-Down Control
W219B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
Notes:
2.
3.
4.
5.
Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W219B.
The shaded sections on the SDRAM, REF, and USB clocks indicate
“
Don
’
t Care
”
states.
Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
0 ns
Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)
40 ns
30 ns
20 ns
10 ns
SDRAM 100 Period
CPU 100 Period
Hub-PC
1
2
Center
0 ns
25 ns
50 ns
75 ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 4. PWRDWN# Timing Diagram
[2, 3, 4, 5]
相关PDF资料 |
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| W22010AJ-12 | x4 SRAM |
| W22010AJ-15 | x4 SRAM |
| W22010AJ-20 | x4 SRAM |
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