参数资料
型号: W24B02B-70LI
厂商: WINBOND ELECTRONICS CORP
元件分类: SRAM
英文描述: 256K X 8 STANDARD SRAM, 70 ns, PBGA48
封装: TFBGA-48
文件页数: 1/11页
文件大小: 194K
代理商: W24B02B-70LI
Preliminary W24B02
256K
× 8 CMOS STATIC RAM
Publication Release Date: May 6, 2002
- 1 -
Revision A1
GENERAL DESCRIPTION
The W24B02 is a normal-speed, very low-power CMOS static RAM organized as 262144 x 8 bits that
operates on a wide voltage range from 2.7V to 3.6V power supply. The W24B02, W24B02-LE and
W24B02
-LI, can meet the requirement of various operating temperature. This device is manufactured
using Winbond’s high performance CMOS technology.
FEATURES
Low power consumption
Access time: 55/70 nS
2.7V to 3.6V supply voltage
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 1.5V (min.)
Available packages: TFBGA and 32-pin Type
one TSOP (8 x 13.4 mm and 8 x 20 mm)
PIN CONFIGURATIONS
TFBGA TOP VIEW
20
1
32-pin
TSOP
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
32
31
30
29
28
27
23
19
18
17
26
25
24
22
21
#OE
A2
I/O8
I/O5
A10
#CS
A0
A3
A1
I/O7
I/O6
I/O4
Vss
I/O3
I/O1
I/O2
A9
A8
A13
#WE
A5
A6
A7
A16
A4
A12
A17
V
A15
A11
A14
NC
1
2
3
4
5
6
A
A0
A1
NC
A3
A6
A8
B
I/O5
A2
#WE
A4
A7
I/O1
C
I/O6
NC
A5
I/O2
D
E
VSS
VDD
DD
V
VSS
F
I/O7
A17
I/O3
G
I/O8
#OE
#CS
A16
A15
I/O4
H
A9
A10
A11
A12
A13
A14
NC
DD
BLOCK DIAGRAM
CORE CELL ARRAY
1024 ROWS
256 X 8 COLUMNS
DATA
CNTRL.
CLK
GEN.
R
O
W
D
E
C
O
D
E
R
A6
I/O CKT.
COLUMN DECODER
#WE
#OE
CLK GEN.
PRECHARGE CKT.
A5 A4 A3 A2 A1 A0
#CS
A18
A17
A16
A15
A14
A13
A12
A10
A8
A7
I/O1
I/O8
:
A9
A11
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
A17
Address Inputs
I/O1
I/O8
Data Inputs/Outputs
#CS
Chip Select Input
#WE
Write Enable Input
#OE
Output Enable Input
VDD
Power Supply
VSS
Ground
NC
No Connection
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