W254B
Document #: 38-07233 Rev. *A
Page 10 of 17
Byte 5 has been provided as an optional register to enable a
greater degree of spread spectrum and overclocking perfor-
mance for all PLL1 outputs. (CPU, SDRAM, DCLK, APIC, PCI,
3V66 and VCH_CLK)
By enabling Byte 5, (bits 5 and 6) spread spectrum can be
increased to +0.5% and /or overclocking of either 5%, 10% or
15% can be enabled.
It is not necessary to access Byte 5 if these additional features
are not implemented. All outputs will default to 0% overclock-
ing upon power up, with either 0% or
–
0.5% spread spectrum.
Byte 3: Control Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
13
12
11
10
8
7
--
Name
Pin Description
Reserved Drive to
’
0
’
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1/FS1
SDRAM 133-MHz Mode Enable
(Active/Inactive)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
Default is Disabled =
‘
0
’
, Enabled =
’
1
’
Byte 4: Control Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Pin#
19
Name
Pin Description
VCH_CLK SSC Mode
0 = 48 MHz non-SSC (default)
1 = 66 MHz SSC
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
(Disabled/Enabled)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
-
Byte 5: Control Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
-
-
Name
Pin Description
Reserved Drive to
‘
0
’
Spread Spectrum and Overclocking
Mode Select. See
Table 9
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
‘
0
’
Reserved Drive to
‘
0
’
-