参数资料
型号: W254B
英文描述: Clocks and Buffers
中文描述: 时钟和缓冲器
文件页数: 6/17页
文件大小: 247K
代理商: W254B
W254B
Document #: 38-07233 Rev. *A
Page 6 of 17
Power-Down Control
W254B provides one PWR_DWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off
and all clock outputs are driven LOW.
Notes:
4.
5.
6.
7.
Once the PWR_DWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W254B.
The shaded sections on the SDRAM, REF, and USB clocks indicate
Don
t Care
states.
Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Table 6. 133 MHz/SDRAM Test Mode Group Timing Relationships and Tolerance
CPU to SDRAM
3.75 ns
500 ps
CPU to 3V66
0.0 ns
500 ps
SDRAM to
3V66
3.75 ns
500 ps
3V66 to
PCI
1.5-3.5 ns
500 ps
PCI to
APIC
0.0 ns
1.0 ns
USB& DOT
Async
N/A
Offset
Tolerance
Table 7. W254B Maximum Allowed Current
W254B
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
V
= 2.625V
All static inputs = V
DDQ3
or V
SS
< 1 mA
Max. 3.3V supply consumption
Max. discrete cap loads
V
= 3.465V
All static inputs = V
DDQ3
or V
SS
< 1 mA
Powerdown Mode
(PWR_DWN# = 0)
Full Active 66 MHz
FS1:0 = 00 (PWR_DWN# =1)
Full Active 100 MHz
FS1:0 = 01 (PWR_DWN# =1)
Full Active 133 MHz
FS1:0 = 11 (PWR_DWN# =1)
70 mA
280 mA
100 mA
280 mA
100 mA
280 mA
1
2
Center
0 ns
25 ns
50 ns
75 ns
VCO Internal
CPU 100-MHz
3V66 66-MHz
PCI 33 MHz
APIC 33-MHz
PwrDwn
SDRAM 100-MHz
REF 14.318-MHz
USB 48-MHz
Figure 6. W254B PWR_DWN# Timing Diagram
[4, 5, 6, 7]
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