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参数资料
| 型号： | W254B |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 9/17页 |
| 文件大小： | 247K |
| 代理商： | W254B |
W254B
Document #: 38-07233 Rev. *A
Page 9 of 17
W254B Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be writ-
ten to a
“
0
”
level.
3. All register bits labeled
“
Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current.
Note:
9.
Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 0: Control Register (1 = Enable, 0 = Disable)
[9]
Bit
Pin#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Pin Description
19
--
43
44
--
22
21
--
VCH_CLK
Reserved Drive to
’
0
’
CPU_F
CPU
Spread Spectrum (1 = On; 0 = Off)
DOT (48 MHz)
USB (48 MHz)
Reserved Drive to
’
0
’
(Active/Inactive)
(Active/Inactive)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
Byte 1: Control Register (1 = Enable, 0 = Disable)
[9]
Bit
Pin#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Pin Description
--
--
33
34
36
37
39
40
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
(Active/Inactive)
(Active/Inactive)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
Byte 2: Control Register (1 = Enable, 0 = Disable)
[9]
Bit
Pin#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Pin Description
17
16
15
--
--
--
--
--
3V66_AGP
3V66_1
3V66_0
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
Reserved Drive to
’
0
’
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
相关PDF资料 |
PDF描述 |
|---|---|
| W255 | Clocks and Buffers |
| W255H | 200-MPz 24-Output Buffer for 4DDR or 3 SDRAM DIMMS |
| W255HT | 200-MPz 24-Output Buffer for 4DDR or 3 SDRAM DIMMS |
| W25P010AD-8 | x32 Fast Synchronous SRAM |
| W25P010AF-6 | x32 Fast Synchronous SRAM |
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|---|---|
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