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参数资料
| 型号： | W25Q40BWSNIG |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 4M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 3.81 MM, GREEN, PLASTIC, SOIC-8 |
| 文件页数： | 50/70页 |
| 文件大小： | 2088K |
| 代理商： | W25Q40BWSNIG |
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W25Q40BW
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8.2.36 Erase Security Registers (44h)
The W25Q40BW offers four 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable
instruction must be executed before the device will accept the Erase Security Register Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the four security registers.
ADDRESS
A23-16
A15-12
A11-8
A7-0
Security Register #0*
00h
0 0 0 0
Don’t Care
Security Register #1
00h
0 0 0 1
0 0 0 0
Don’t Care
Security Register #2
00h
0 0 1 0
0 0 0 0
Don’t Care
Security Register #3
00h
0 0 1 1
0 0 0 0
Don’t Care
* Please note that Security Register 0 is Reserved by Winbond for future use. It is
recommended to use Security registers 1- 3 before using register 0.
The Erase Security Register instruction sequence is shown in figure 34. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time
duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read
Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is
a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-0) in the Status
Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the
corresponding security register will be permanently locked, Erase Security Register instruction to that
register will be ignored (See 8.1.9 for detail descriptions).
Figure 34. Erase Security Registers Instruction Sequence
Instruction (44h)
相关PDF资料 |
PDF描述 |
|---|---|
| WS512K32-25HI | 2M X 8 MULTI DEVICE SRAM MODULE, 25 ns, CHIP66 |
| WS512K32N-70HI | 2M X 8 MULTI DEVICE SRAM MODULE, 70 ns, CHIP66 |
| WF128K32-60G4I5 | 512K X 8 FLASH 5V PROM MODULE, 60 ns, CQFP68 |
| WMS128K8-17FME | 128K X 8 STANDARD SRAM, 17 ns, CDFP36 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W25Q40BWSNIG TR | 制造商:Winbond Electronics Corp 功能描述:IC FLASH 4MBIT 80MHZ 8SOIC |
| W25Q40BWSNIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:1.8V 4M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q40BWSSIG | 功能描述:IC FLASH SPI 4MBIT 8SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 系列:SpiFlash® 标准包装:2,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:256K (32K x 8) 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:28-TSSOP（0.465"，11.8mm 宽） 供应商设备封装:28-TSOP 包装:带卷 (TR) 其它名称:71V256SA15PZGI8 |
| W25Q40BWSSIG TR | 制造商:Winbond Electronics Corp 功能描述:IC FLASH 4MBIT 80MHZ 8SOIC |
| W25Q40BWUXIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:1.8V 4M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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