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参数资料
| 型号： | W28V400 |
| 英文描述： | FLASH |
| 中文描述： | 闪光 |
| 文件页数： | 14/48页 |
| 文件大小： | 427K |
| 代理商： | W28V400 |
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W28V400B/T
- 14 -
Table 4. Identifier Codes
CODE
ADDRESS [A17
A0]
DATA [DQ7
DQ0]
Manufacture Code
00000H
B0H
Top Boot
58H
Device Code
Bottom Boot
00001H
5AH
Read Status Register Command
The status register may be read to determine when a block erase or word/byte write is complete and
whether the operation completed successfully. It may be read at any time by writing the Read Status
Register command. After writing this command, all subsequent read operations output data from the
status register until another valid command is written. The status register contents are latched on the
falling edge of #OE or #CE, whichever occurs last. #OE or #CE must toggle to V
IH
before further reads
to update the status register latch. The Read Status Register command functions independently of the
V
PP
voltage. #RESET can be V
IH
or V
HH
.
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate various failure conditions (see Table 7). By
allowing system software to reset these bits, several operations (such as cumulatively erasing multiple
blocks or writing several words/bytes in sequence) may be performed. The status register may be
polled to determine if an error occurred during the sequence. To clear the status register, the Clear
Status Register command (50H) is written. It functions independently of the applied V
PP
voltage.
#RESET can be V
IH
or V
HH
.
This command is not functional during block erase or word/byte write
suspend modes.
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm. This command sequence requires appropriate
sequencing and an address within the block to be erased (all bits within the block being set to “1”).
Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the device automatically outputs status register
data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output
data of the RY/#BY pin or status register bit SR.7.
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued.
This two-step command sequence of set-up followed by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command sequence will result in both status register bits
SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when V
DD
= V
DD1/2/3/4
and
V
PP
= V
PPH1/2/3
. In the absence of this high voltage, block contents are protected against erasure.
If block erase is attempted while V
PP
≤
V
PPLK
, SR.3 and SR.5 will be set to "1". Successful block erase
for boot blocks requires that the corresponding if set, that #WP = V
IH
or #RESET = V
HH
. If block erase
is attempted to boot block when the corresponding #WP = V
IL
or #RESET = V
IH
, SR.1 and SR.5 will be
set to "1". Block erase operations with V
IH
< #RESET < V
HH
produce spurious results and should not
be attempted.
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相关代理商/技术参数 |
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|---|---|
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