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| 型号： | W3E32M64S-400SBC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM, 0.7 ns, PBGA208 |
| 封装： | 13 X 22 MM, PLASTIC, BGA-208 |
| 文件页数： | 4/17页 |
| 文件大小： | 615K |
| 代理商： | W3E32M64S-400SBC |
12
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E32M64S-XSBX
November 2005
Rev. 3
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 1-5, 14-17, 33)
Parameter
Symbol
400Mbx CL3
(54)
333 Mbs CL
3 (53)
266 Mbs CL2.5
266 Mbs CL 2.5
200 Mbs CL2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Access window of DQs from CLK/CLK#
tAC
-0.7
+0.7
-0.70
+0.70
-0.75
+0.75
-0.8
+0.8
-0.8
+0.8
ns
CLK high-level width (30)
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CLK low-level width (30)
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock cycle time
CL = 3 (45, 51, 53)
tCK (3)
5
7.5
6
13
------
ns
CL = 2.5 (45, 51)
tCK (2.5)
7.5
13
7.5
13
7.5
13
8
13
10
13
ns
CL = 2 (45, 51)
tCK (2)
-
1013101310131315
ns
DQ and DM input hold time relative to DQS (26, 31)
tDH
0.4
0.45
0.5
0.6
ns
DQ and DM input setup time relative to DQS (26, 31)
tDS
0.4
0.45
0.5
0.6
ns
DQ and DM input pulse width (for each input) (31)
tDIPW
1.75
2
ns
Access window of DQS from CLK/CLK#
tDQSCK
-0.6
+0.6
-0.6
+0.6
-0.75
+0.75
-0.8
+0.8
-0.8
+0.8
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
tDQSQ
0.4
0.45
0.5
0.6
ns
Write command to rst DQS latching transition
tDQSS
0.72
1.28
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CLK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CLK rising - hold time
tDSH
0.2
tCK
Half clock period (34)
tHP
tCH,tCL
ns
Data-out high-impedance window from CLK/CLK# (18, 42)
tHZ
+0.70
+0.75
+0.8
ns
Data-out low-impedance window from CLK/CLK# (18, 42)
tLZ
-0.70
-0.75
-0.8
ns
Address and control input hold time (fast slew rate)
tIHF
0.6
0.75
0.90
1.1
ns
Address and control input setup time (fast slew rate)
tISF
0.6
0.75
0.90
1.1
ns
Address and control input hold time (slow slew rate) (14)
tIHS
-
0.8
1
1.1
ns
Address and control input setup time (slow slew rate) (14)
tISS
-
0.8
1
1.1
ns
Address and control input pulse width (for each input)
tIPW
2.2
---------
ns
LOAD MODE REGISTER command cycle time
tMRD
10
12
15
16
ns
DQ-DQS hold, DQS to rst DQ to go non-valid, per access (25, 26)
tQH
tHP-tQHS
ns
Data hold skew factor
tQHS
0.5
0.55
0.75
1
ns
ACTIVE to PRECHARGE command (35)
tRAS
40
70,000
42
70,000
40
120,000
40
120,000
40
120,000
ns
ACTIVE to READ with Auto precharge command (46)
tRAP
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
55
60
65
70
ns
AUTO REFRESH command period (49)
tRFC
70
72
75
80
ns
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
PRECHARGE command period
tRP
15
20
ns
DQS read preamble (43)
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble (43)
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time (20, 21)
tWPRES
00000
ns
DQS write postamble (19)
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
21111
tCK
Data valid output window (25)
NA
tQH - tDQSQ
ns
REFRESH to REFRESH command interval (23) (commercial and
Industrial)
tREFC
70.3
μs
REFRESH to REFRESH command interval (Military temperature)
tREFC
35
μs
Average periodic refresh interval (23) (commercial and Industrial)
tREFI
7.8
μs
Average periodic refresh interval (Military temperature)
tREFI
-
3.9
μs
Terminating voltage delay to VDD
tVTD
00000
ns
Exit SELF REFRESH to non-READ command
tXSNR
70
75
80
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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| W3E32M64SA-200BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
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