- 您现在的位置：买卖IC网 > PDF目录68451 > W3E64M72S-200SBC (WHITE ELECTRONIC DESIGNS CORP) 64M X 72 DDR DRAM, 0.8 ns, PBGA219 PDF资料下载
参数资料
| 型号： | W3E64M72S-200SBC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| 封装： | 25 X 32 MM, PLASTIC, BGA-219 |
| 文件页数： | 18/19页 |
| 文件大小： | 496K |
| 代理商： | W3E64M72S-200SBC |
W3E64M72S-XSBX
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2007
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE 1 – BURST DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0
selects the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1
select the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
FIGURE 3 – MODE REGISTER DEFINITION
M3 = 0
2
4
8
Reserved
M3 = 1
2
4
8
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
Valid
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Operating Mode
A10
A11
* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
0*
BA0
BA1
Reserved
3
M9
M10
M11
0
10
0
--
-
A12
M12
0
-
14
13
12 11 10
9
8
7
6
5
4
3
2
1
0
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was issued at the earliest possible
time, without violating tRAS (MIN).The user must not issue
another command to the same bank until the precharge
time (tRP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO
REFRESH command is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. Each DDR SDRAM
相关PDF资料 |
PDF描述 |
|---|---|
| W3E64M72S-333SBC | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-266SBM | 64M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E64M72S-333BC | 64M X 72 SYNCHRONOUS DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-250BM | 64M X 72 SYNCHRONOUS DRAM, 0.8 ns, PBGA219 |
| W3EG128M72ETSU262JD3 | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3E64M72S-200SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR, 2.5V, 200 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E64M72S-200SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR, 2.5V, 200 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E64M72S-250BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-250BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-250BM | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
发布紧急采购，3分钟左右您将得到回复。