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参数资料
| 型号： | W3EG2256M72ASSR202AJD3SG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 512M X 72 DDR DRAM MODULE, 0.8 ns, DMA184 |
| 封装： | ROHS COMPLIANT, DIMM-184 |
| 文件页数： | 11/14页 |
| 文件大小： | 309K |
| 代理商： | W3EG2256M72ASSR202AJD3SG |
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
6
White Electronic Designs
March, 2007
Rev. 4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
IDD1 : OPERATING CURRENT: ONE BANK
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lOUT = 0mA
4. Timing patterns
DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,
tRCD = 2*tCK, tRAg = 5*tCK
Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5,
BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
IDD7A: OPERATING CURRENT: FOUR BANKS
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA
4. Timing patterns
DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,
tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every burst
DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with
autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2, BL
= 4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
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