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参数资料
| 型号： | W3EG72128S265AD4-SG |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封装： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件页数： | 10/14页 |
| 文件大小： | 197K |
| 代理商： | W3EG72128S265AD4-SG |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG72128S-AD4
-BD4
August 2005
Rev. 3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR333@CL=2.5
Max
DDR266@CL=2
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
2620
mA
Operating Current
IDD1
One device bank; Active-Read-
Precharge; Burst = 2; tRC=tRC(MIN)
;tCK=tCK(MIN); Iout = 0mA; Address
and control inputs changing once per
clock cycle.
2890
mA
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power- down
mode; tCK=tCK(MIN); CKE=(low)
90
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. Vin = Vref for
DQ, DQS and DM.
1085
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down
mode; tCK(MIN); CKE=(low)
630
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One
device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per
clock cycle.
1175
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst;
One device bank active;Address
and control inputs changing once
per clock cycle; tCK=tCK(MIN); Iout
= 0mA.
2935
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK(MIN); DQ,DM
and DQS inputs changing twice per
clock cycle.
3025
2845
mA
Auto Refresh Current
IDD5
tRC=tRC(MIN)
4060
mA
Self Refresh Current
IDD6
CKE
≤ 0.2V
360
365
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK(MIN); Address and
control inputs change only during
Active Read or Write commands.
5095
5050
mA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3EG72128S265AD4-XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG72128S265BD4-XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG72128S265D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM UNBUFFERED |
| W3EG72128S265JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM UNBUFFERED |
| W3EG72128S335AD4-XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
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