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参数资料
| 型号： | W3EG7266S202D3G |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 2/12页 |
| 文件大小： | 173K |
| 代理商： | W3EG7266S202D3G |
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7266S-D3
October 2005
Rev. 3
PRELIMINARY
11.
It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on tDQSS.
12.
The refresh period is 64ms. This equates to an average refresh
rate of 15.625s or 7.8125s. However, an AUTO REFRESH
command must be asserted at least once every 140.6s or
70.3s; burst refreshing or posting by the DRAM controller greater
than eight refresh cycles is not allowed.
13.
The valid data window is derived by achieving other specications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
14.
Referenced to each output group: x4 = DQS with DQ0-DQ4.
15.
READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satised prior to the internal precharge
command being issued.
16.
JEDEC species CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17.
DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to tDS and tDH for each
100mV/ns reduction in slew rate. If slew rates exceeds 4V/ns,
functionality is uncertain.
18.
tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
19.
This maximum value is derived from the referenced test load. In
practice, the values obtained in a typical terminated design may
reect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will
prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN)
will prevail over tDQSCK (MIN) + PRE (MAX) condition.
20.
For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
21.
CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tREF later.
22.
Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
Notes
1.
All voltages referenced to VSS
2.
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specications and device operations are guaranteed for
the full voltage range specied.
3.
Outputs are measured with equivalent load:
Output
(V
(VOUT
OUT
)
Reference
Point
50
VTT
TT
30pF
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specications
are guaranteed for the specied AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5.
The AC and DC input level specications are dened in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
6.
Command/Address input slew rate = 0.5V/ns. For -75 with slew
rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the
slew rate is less than 0.5V/ns, timing must be derated: tIS has an
additional 50ps per each 100mV/ns reduction in slew rate from the
500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain.
7.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE
≤ 0.3 x VCC is
recognized as LOW.
8.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specic voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
9.
The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
10.
This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
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相关代理商/技术参数 |
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| W3EG7266S262AD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
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