参数资料
型号: W3H64M16E-400BC
厂商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分类: DRAM
英文描述: 64M X 16 DDR DRAM, 0.6 ns, PBGA79
封装: 14 X 11 MM, 1.27 MM PITCH, PLASTIC, BGA-79
文件页数: 27/30页
文件大小: 881K
代理商: W3H64M16E-400BC
W3H64M16E-XBX
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
July 2009
Rev. 5
White Electronic Designs Corp. reserves the right to change products or specications without notice.
low level must be applied to the ODT ball (all other
inputs may be undened, I/Os and outputs must be
less than VCCQ during voltage ramp time to avoid DDR2
SDRAM device latch-up). At least one of the following
two sets of conditions (A or B) must be met to obtain a
stable supply state (stable supply dened as VCC, VCCQ,
VREF, and VTT are between their minimum and maximum
values as stated in Table 5):
A. (single power source) The VCC voltage ramp
from 300mV to VCC (MIN) must take no longer
than 200ms; during the VCC voltage ramp, |VCC
-
VCCQ| ≤ 0.3V. Once supply voltage ramping
is complete (when VCCQ crosses VCC (MIN)),
Table20 specications apply.
VCC, VCCQ are driven from a single power
converter output
VTT is limited to 0.95V MAX
VREF tracks VCCQ/2; VREF must be within
±0.3V with respect to VCCQ/2 during supply
ramp time
VCCQ ≥ VREF at all times
B. (multiple power sources) VCC ≥ VCCQ must be
maintained during supply voltage ramping, for
both AC and DC levels, until supply voltage
ramping completes (VCCQ crosses VCC [MIN]).
Once supply voltage ramping is complete,
Table 5 specications apply.
Apply VCC before or at the same time as
VCCQ; VCC voltage ramp time must be ≤
200ms from when VCC ramps from 300mV to
VCC (MIN)
Apply VCCQ before or at the same time as
VTT; the VCCQ voltage ramp time from when
VCC (MIN) is achieved to when VCCQ (MIN)
is achieved must be ≤ 500ms; while VCC is
ramping, current can be supplied from VCC
through the device to VCCQ
VREF must track VCCQ/2, VREF must be within
±0.3V with respect to VCCQ/2 during supply
ramp time; VCCQ ≥ VREF must be met at all
times
Apply VTT; The VTT voltage ramp time from
when VCCQ (MIN) is achieved to when VTT
(MIN) is achieved must be no greater than
500ms
2.
For a minimum of 200μs after stable power and
clock (CK, CK#), apply NOP or DESELECT
commands and take CKE HIGH.
3.
Wait a minimum of 400ns, then issue a
PRECHARGE ALL command.
4.
Issue an LOAD MODE command to the EMR(2).
(To issue an EMR(2) command, provide LOW to
BA0 and BA2, provide HIGH to BA1.)
5.
Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0
and BA1, provide LOW to BA2.)
6.
Issue an LOAD MODE command to the EMR to
enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1, BA2 and A0, provide HIGH to
BA0. Bits E7, E8, and E9 can be set to “0” or “1”; it
is recommended to setting them to “0.”
7.
Issue a LOAD MODE command for DLL RESET.
200 cycles of clock input is required to lock the DLL.
(To issue a DLL RESET, provide HIGH to A8 and
provide LOW to BA2, BA1, and BA0.) CKE must be
HIGH the entire time.
8.
Issue PRECHARGE ALL command.
9.
Issue two or more REFRESH commands.
10. Issue a LOAD MODE command with LOW to A8 to
initialize device operation (i.e., to program operating
parameters without resetting the DLL).
11. Issue a LOAD MODE command to the EMR to
enable OCD default by setting bits E7, E8, and E9
to “1,” and then setting all other desired parameters.
12. Issue a LOAD MODE command to the EMR to
enable OCD exit by setting bits E7, E8, and E9 to
“0,” and then setting all other desired parameters.
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W3H64M64E-400SBM 制造商:Microsemi Corporation 功能描述:64M X 64 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY
W3H64M64E-533SBC 制造商:Microsemi Corporation 功能描述:64M X 64 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk