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参数资料
| 型号： | W6694ACD |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件页数： | 22/42页 |
| 文件大小： | 567K |
| 代理商： | W6694ACD |
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Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-29-
Publication Release Date: May, 2001
Revision 1.03
GRLP GCI Mode Remote Loop back
Setting this bit to 1 activates the remote loop back function. The 2B+D channels data received from the GCI bus
interface are looped to the transmitted channels.
SPU
Software Power Up
PD
Power Down
SPU
PD
Description
0
1
After U transceiver power down, W6694A will receive the indication DC (Deactivation Confirmation) from
GCI bus and then software has to set SPU
→ 0, PD →1 to acknowledge U transceiver, by pulling GCIDU
line to HIGH. W6694A remains normal operation.
1
0
Setting SPU
→ 1, PD →0 will pull the GCI bus GCIDU line to LOW. This will enforce connected layer 1
devices (U transceiver) to deliver GCI bus clocking.
0
After reception of the indication PU (Power Up indication) the reaction of the microprocessor should be:
- To write an AR (Activate Request command) as C/I command code in the CIX register.
- To reset the SPU bit and wait for the following ICC (indication code change) interrupt.
1
Unused.
GE
GCI Mode Enable
Setting this bit to 1 will enable the GCI bus interface. In the same time, the S/T layer 1 function is disabled.
8.3.2 Monitor Channel Control Register
MOCR
Read/Write
Address 07h
Value after reset: 00h
7
6
5
4
3
2
1
0
MRIE
MRC
MXIE
MXC
MRIE
Monitor Channel 0 Receive Interrupt Enable
Monitor channel interrupt status MDR, MER generation is enabled (1) or masked (0).
MRC
MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRIE=1).
1: MR internally controlled according to Monitor channel protocol. In addition, the MDR interrupt is enabled for all
bytes according to the Monitor channel protocol (if MRIE=1).
MXIE
Monitor Channel Transmit Interrupt Enable
Monitor interrupt status MDA, MAB generation is enabled (1) or masked (0).
MXC
MX Bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled according to Monitor channel protocol.
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