参数资料
型号: W942516CH-75
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: 16M X 16 DDR DRAM, 0.75 ns, PDSO66
封装: 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件页数: 15/47页
文件大小: 2809K
代理商: W942516CH-75
W942516CH
- 22 -
The write command performs a Write operation to the bank designated by BS. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.
5. Write with Auto Precharge Command
( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column
Address)
The Write with Auto Precharge command performs the Precharge operation automatically after the
Write operation. This command must not be interrupted by any other commands.
6. Read Command
( RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column
Address)
The Read command performs a Read operation to the bank designated by BS. The read data are
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode
and CAS Latency (access time from CAS command in a clock cycle) must be programmed in
the Mode Register at power-up prior to the Read operation.
7. Read with Auto Precharge Command
( RAS = "H", CAS = ”L”, WE = ”H”, BS0, BS1 = Bank, A10 = ”H”, A0 to A9, A11 = Column
Address)
The Read with Auto precharge command automatically performs the Precharge operation after the
Read operation.
1) READA
tRAS (min) - (BL/2) x tCK
Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command.
2) tRCD(min)
READA < tRAS(min) - (BL/2) x tCK
Data can be read with shortest latency, but the internal Precharge operation does not begin until
after tRAS (min) has completed.
This command must not be interrupted by any other command.
8. Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data)
The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after power-
up are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.
9. Extended Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data)
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