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Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.11 DTE Discovery Process
4.11.1
Definitions
The terms in
Table 47 are used throughout the DTE discovery sections:
4.11.2
Interaction between Processor, MAC, and PHY
The state machines that control the mechanics of the Discovery process reside within the
LXT9785E device. However, control of the power supply and overall system control reside
in the system processor. The processor communicates with the power supply unit (PSU)
and switches it on and off dependant on the data that is supplied by the PHY. The PHY
register data is read by the MAC using the MDIO interface. The required control bits are
contained in the PHY device register map and are discussed in detail in the section
Note:
The details of the processor/MAC interface and the processor/PSU interface are
implementation specific and therefore are out of the scope of this specification.
The following is an overview of the system control for a successful Remote-Power DTE
discovery:
1. The discovery process is enabled by the DTE Discovery Process Enable (Dis_EN)
Register bit 27.6 and the Auto-Negotiation Enable Register bit 0.12. Writing Register
bit 27.6 immediately affects the Auto-Negotiation Base Page. If already enabled, auto-
negotiation should be restarted after this bit is written to ensure proper operation.
Register bit 4.15 is used for manual control of auto-negotiation next pages and should
be left in the default state (cleared).
2. The LXT9785E PHY then tests to see if a Remote-Power DTE is present as the link
partner. If a Remote-Power DTE is found, the Power Enable (Power_EN) Register bit
27.4 is set. The processor polls this signal via the MAC.
3. Upon detecting a Remote-Power DTE, the processor instructs the power supply to
switch on. Once power has been applied to the DTE, normal negotiation takes place.
The processor must enable the required negotiation process by restarting auto-
negotiation, or by setting forced speed mode after power has been applied. The
processor must poll the link-up Register bit 1.2 for the corresponding LXT9785E port,
or the link status change interrupt, to ensure that the link has been established.
4. A time-out must be connected with this feature so that if link is not established within a
pre-determined time period (system dependant), the processor instructs the power
supply to switch off. If link is not established prior to the expiration of the “link fail
inhibit timer”, the LXT9785E restarts negotiation with DTE detection if auto-
Table 47
DTE Terms
Term
Definition
Negotiation Process:
This includes auto-negotiation and parallel detection processes
System:
The switch system using the LXT9785E for DTE Discovery
Link Partner:
A device connected to the LXT9785E through twisted pair cables
DTE:
Data Terminal Equipment; any end-of-link partner
Standard Link Partner:
A link partner that is not requiring power over a Category 5 cable; typically a PC
Remote-Power DTE:
Data Terminal Equipment requiring power over a Category 5 cable; typically an
IP telephone
Discovery:
The process of identifying the type of link partner present