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参数资料
| 型号： | WE128K32P-125H1I |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 125 ns, CPGA66 |
| 封装： | 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66 |
| 文件页数： | 9/14页 |
| 文件大小： | 496K |
| 代理商： | WE128K32P-125H1I |
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WE128K32-XXX
March 2008
Rev. 12
White Electronic Designs Corp. reserves the right to change products or specications without notice.
WRITE
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs rst. A byte write operation will
automatically continue to completion.
write cycle timing
Figures 5 and 6 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
The WE# line transition from high to low also initiates
an internal 150 μsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 μsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Write Cycle Parameter
Symbol
Min
Max
Unit
Write Cycle Time, TYP = 6ms
tWC
10
ms
Address Set-up Time
tAS
0ns
Write Pulse Width (WE# or CS#)
tWP
100
ns
Chip Select Set-up Time
tCS
0ns
Address Hold Time
tAH
100
ns
Data Hold Time
tDH
10
ns
Chip Select Hold Time
tCSH
0ns
Data Set-up Time
tDS
50
ns
Output Enable Set-up Time
tOES
0ns
Output Enable Hold Time
tOEH
0ns
Write Pulse Width High
tWPH
50
ns
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