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参数资料
| 型号： | WED2DL36513V40BI |
| 元件分类： | SRAM |
| 英文描述： | 512K X 36 MULTI DEVICE SRAM MODULE, 4 ns, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 6/12页 |
| 文件大小： | 266K |
| 代理商： | WED2DL36513V40BI |
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL36513V
WED2DL36513AV
INTERLEAVED BURST TABLE (MODE = NC OR HIGH)
First Address
Second Address
Third Address
Fourth Address
External
Internal
X...X00
X...X01
X...X10
X...X11
X...X01
X....X00
X...X11
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
INTERLEAVED BURST TABLE (MODE = LOW)
First Address
Second Address
Third Address
Fourth Address
External
Internal
X...X00
X...X01
X...X10
X...X11
X...X01
X....X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
TRUTH TABLE
Function
Address
CE
CE2
ZZ
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Used
Deselected Cycle,Power-Down
None
H
X
L
X
L
X
L-H
High-Z
Deselected Cycle,Power-Down
None
L
X
L
X
L-H
High-Z
Deselected Cycle,Power-Down
None
L
H
X
L
X
L-H
High-Z
Deselected Cycle,Power-Down
None
L
X
L
H
L
X
L-H
High-Z
Deselected Cycle,Power-Down
None
L
H
X
L
H
L
X
L-H
High-Z
SNOOZE MODE,Power-Down
None
X
H
X
High-Z
READ Cycle, Begin Burst
External
L
H
L
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
X
H
L-H
High-Z
WRITE Cycle Begin Burst
External
L
H
L
H
L
X
L
X
L-H
D
READ Cycle Begin Burst
External
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle Begin Burst
External
L
H
L
H
L
X
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
L
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
L
H
L
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
L
H
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
L
X
H
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
L
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
L
H
HHHH
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
L
X
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
L
X
HHHH
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
L
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
L
X
H
L
X
L-H
D
NOTES:
1. X means “Don’t Care.” —— means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW
HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s
and DQPd.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW
LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
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