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| 型号： | WHITEPAPER |
| 英文描述： | White Paper - The Mobile AMD Athlon XP Processor |
| 中文描述： | 白皮书-移动AMD Athlon XP处理器 |
| 文件页数： | 2/17页 |
| 文件大小： | 102K |
| 代理商： | WHITEPAPER |
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The Mobile AMD Athlon XP-M Processor
March 2003
can execute. In order to continually feed the execution engine with data, the mobile
AMD Athlon XP-M processor includes three x86 instruction decoders. Each decoder is
capable of decoding three instructions per clock cycle. In comparison, the Pentium 4
is designed to decode only one instruction per clock cycle with the resource of only
one x86 instruction decoder. Thus, the Pentium 4 has only one-third the maximum
theoretical decode bandwidth of the mobile AMD Athlon XP-M processor. The decode
bandwidth of the mobile AMD Athlon XP-M processor enables the processor to
advantageously utilize the execution bandwidth capabilities of QuantiSpeed
architecture, thereby improving IPC.
QuantiSpeed Architecture: Superscalar Fully Pipelined
x86 Floating Point Unit (FPU)
The mobile AMD Athlon XP-M processor offers one of the most powerful,
architecturally advanced floating-point units (FPU) delivered in an x86 microprocessor.
The mobile AMD Athlon XP-M processor’s three-issue, superscalar floating-point
capability is based on three pipelined, out-of-order floating-point execution units,
each with a one-cycle throughput. Using a data format and single-instruction
multiple-data (SIMD) operations based on the MMX instruction model, the mobile
AMD Athlon XP-M processor can deliver as many as four 32-bit, single-precision
floating-point results per clock cycle.
FPU Microarchitecture
Three separate execution units in the mobile AMD Athlon XP-M processor’s
floating-point pipeline support x87 floating-point instructions, MMX instructions, and
3DNow! Professional technology instructions. The three execution units are:
1) Fstore—This is the floating point load/store pipeline that handles FP
loads, stores, and miscellaneous operations.
2) Fadd—This is the adder pipeline that contains 3DNow! Professional
technology, add, MMX ALU/shifter, and FP add execution units.
3) Fmul—This is the multiplier pipeline that contains an MMX ALU, MMX
multiplier, reciprocal unit, FP, 3DNow! Professional technology instruction
multiplier, and support for FDIV instructions.
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