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| 型号： | WHITEPAPER |
| 英文描述： | White Paper - The Mobile AMD Athlon XP Processor |
| 中文描述： | 白皮书-移动AMD Athlon XP处理器 |
| 文件页数： | 6/17页 |
| 文件大小： | 102K |
| 代理商： | WHITEPAPER |
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The Mobile AMD Athlon XP-M Processor
March 2003
Benefits of the mobile AMD Athlon XP-M processor’s hardware data
prefetching are observed more in high-end, data-intensive applications that access
larger arrays of data. Performance also benefits by not occupying processor
instruction execution bandwidth required by software prefetching instructions. The
optimization is most effective when coupled with high-bandwidth system memory
transfer capability, now available to the processor by platforms such as those
optimized to support DDR memory.
QuantiSpeed Architecture: Exclusive and Speculative
Translation Look-aside Buffers (TLBs)
The mobile AMD Athlon XP-M processor features advanced, two-level
Translation Look-aside Buffer (TLB) structures for both instruction and data address
translation. The mobile AMD Athlon XP-M processor’s Level 1 (L1) Instruction TLB
(I-TLB) holds 24 entries, the L1 Data TLB (D-TLB) holds 40 entries, and the L2 I-TLB
and D-TLB each hold 256 entries.
To reduce the incidence of TLB entry conflicts, the L1 and L2 TLB structures
adopt an exclusive architecture design. With an exclusive TLB architecture, the L1
TLBs can contain entries that are not duplicated in the L2 TLBs, enabling the
combination of L1 TLB and L2 TLB sizes for a larger total available entry space on
both the instruction and data TLBs. By reducing the number of conflicts caused by
holding more TLB entries within the processor, performance increases on high-end,
data-intensive applications that encounter instruction sequences that no longer have
to wait for TLB entries to be reloaded during execution.
The TLB structures of the mobile AMD Athlon XP-M processor also have the
ability to enter data TLB misses in the TLBs speculatively. The mobile AMD Athlon XP-M
processor allows TLB entries to be written speculatively before the first instruction is
completed, while preserving proper instruction execution ordering which removes the
serialization effect and results in improved system performance.
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