参数资料
型号: WJLXT905LE.C2
厂商: CORTINA SYSTEMS INC
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP32
封装: ROHS COMPLIANT, MO-136BC, LQFP-32
文件页数: 18/40页
文件大小: 544K
代理商: WJLXT905LE.C2
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Datasheet
25
Document Number: 249271
Revision Number: 004
Revision Date: 19-Oct-2005
Table 10. RCLK/Start-of-Frame Timing
Parameter
Symbol
Min
Typ1
Max
Units
Decoder acquisition time
tDATA
–1300
1500
ns
CD turn-on delay
tCD
400
550
ns
Receive data setup from
RCLK
Mode 1
tRDS
60
70
ns
Modes 2, 3, and 4
tRDS
30
45
ns
Receive data hold from RCLK
Mode 1
tRDH
10
20
ns
Modes 2, 3, and 4
tRDH
30
45
ns
RCLK shut off delay from CD assert (Mode 3)
tsws
±100
ns
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
Table 11. RCLK/End-of-Frame Timing
Parameter
Type
Sym
Mode 1
Mode 2
Mode 3
Mode 4
Units
RCLK after CD off
Min
tRC
51
5
BT
Rcv data through-put delay
Max
tRD
400
375
ns
CD turn-off delay 2
Max
tCDOFF
500
475
ns
Receive block out after TEN off
3
Typical
1
tIFG
550
BT
RCLK switching delay after CD
off
Typical
1
tswe
120 (±80)
ns
1. Typical figures are at 25 °C, are for design aid only are not guaranteed, and are not subject to production
testing.
2. CD Turnoff delay, measured from the middle of the last bit: timing specification. The value of the last bit
does not affect this value.
3. Disables blocking of Carrier Detect during full-duplex operation.
Table 12. Transmit Timing
Parameter
Symbol
Minimum
Typical
1
Maximum
Units
TEN setup from TCLK
tEHCH
22
ns
TXD setup from TCLK
tDSCH
22
ns
TEN hold after TCLK
tCHEL
5–
ns
TXD hold after TCLK
tCHDU
5–
ns
Transmit start-up delay
tSTUD
350
450
ns
Transmit through-put delay
tTPD
338
350
ns
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
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