参数资料
型号: WJLXT972ALC.A4SE000
厂商: CORTINA SYSTEMS INC
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: LEAD FREE, LQFP-64
文件页数: 53/100页
文件大小: 1046K
代理商: WJLXT972ALC.A4SE000
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
56
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
Figure 34. Power-Up Timing
Table 35. Power-Up Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Voltage threshold
v1
2.9
V
Power Up delay2
t1
300
s–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Power Up Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY
comes out of reset after a delay of No MORE Than 300
s. System designers should consider this as a minimum
value - After threshold v1 is reached, the MAC should delay No LESS Than 300
s before accessing the MDIO port.
Figure 35. RESET Pulse Width and Recovery Timing
Table 36. RESET Pulse Width and Recovery Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
RESET pulse width
t1
10
ns
RESET recovery delay2
t2
300
s–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the
PHY comes out of reset after a delay of No MORE Than 300
s. System designers should consider this as a minimum
value - After de-asserting RESET*, the MAC should delay No LESS Than 300
s before accessing the MDIO port.
t1
VCC
MDIO,etc
v1
t2
RESET
MDIO,etc
t1
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