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| 型号： | WJLXT972ALC.A4SE001 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 10/100页 |
| 文件大小： | 1046K |
| 代理商： | WJLXT972ALC.A4SE001 |
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Datasheet
17
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
3.0
Functional Description
3.1
Introduction
The LXT972A is a single-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and
100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT972A
can directly drive either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185
meters).
3.1.1
Comprehensive Functionality
The LXT972A provides a standard Media Independent Interface (MII) for 10/100 MACs. The
LXT972A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also
performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.
On power-up, the LXT972A reads its configuration pins to check for forced operation settings. If
not configured for forced operation, it uses auto-negotiation/parallel detection to automatically
determine line operating conditions. If the PHY device on the other side of the link supports auto-
negotiation, the LXT972A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY
partner does not support auto-negotiation, the LXT972A automatically detects the presence of
either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions
accordingly.
The LXT972A provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
3.1.2
OSP Architecture
Intel's LXT972A incorporates high-efficiency Optimal Signal Processing design techniques,
combining the best properties of digital and analog signal processing to produce a truly optimal
device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results
in improved receiver noise and cross-talk performance.
The OSP signal processing scheme also requires substantially less computational logic than
traditional DSP-based designs. This lowers power consumption and also reduces the logic
switching noise generated by DSP engines. This logic switching noise can be a considerable source
of EMI generated on the device’s power supplies.
The OSP-based LXT972A provides improved data recovery, EMI performance and low power
consumption.
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| WJLXT972MLC.A4 | 功能描述:IC TRANS 3.3V ETHERNET 48-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| WJLXT972MLC.A4 S L7U9 | 制造商:Intel 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP |
| WJLXT972MLC.A4-864115 | 功能描述:TXRX ETH 10/100 SGL PORT 48-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF) |
| WJLXT972MLCA4 | 制造商:Cortina Systems Inc 功能描述: |
| WJM1000 | 功能描述:射频模块 902-928 MHz US ISM EPC Class 1 Gen 2 RoHS:否 制造商:Linx Technologies 产品:Transceiver Modules 频带:902 MHz to 928 MHz 输出功率:- 15.5 dBm to + 12.5 dBm 接口类型:UART 工作电源电压:- 0.3 VDC to + 5.5 VDC 传输供电电流:38.1 mA 接收供电电流:22.7 mA 天线连接器类型:U.FL 最大工作温度:+ 85 C 尺寸:1.15 mm x 0.63 mm x 0.131 mm |
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