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| 型号： | WJLXT972ALC.A4SE001 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 15/100页 |
| 文件大小： | 1046K |
| 代理商： | WJLXT972ALC.A4SE001 |
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Datasheet
21
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
3.3
Operating Requirements
3.3.1
Power Requirements
The LXT972A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and
analog circuits require 3.3 V supplies (VCCD and VCCA). These inputs may be supplied from a
single source. Each supply input must be decoupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5 V or
+3.3 V. The inputs on the MII interface are tolerant to 5 V signals from the controller on the other
side of the MII interface. Refer to Table 20 on page 46 for MII I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible.
3.3.2
Clock Requirements
3.3.2.1
External Crystal/Oscillator
The LXT972A requires a reference clock input that is used to generate transmit signals and recover
receive signals. It may be provided by either of two methods: by connecting a crystal across the
oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of
a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is
recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the
LXT971A/972A Design and Layout Guide for a list of recommended clock sources.
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. Refer to Table 21 on page 46 for clock timing
requirements
3.3.2.2
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. Refer to Table 34 on page 55 for details.
Figure 5. Interrupt Logic
Force Interrupt
Interrupt Enable
Event X Mask Reg
Event X Status Reg
Interrupt Pin
...
AND
OR
NAND
Per Event
1. Interrupt (Event) Status Register is cleared on read.
(MDINT)
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