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| 型号： | WJLXT972MLC.A4-864101 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP48 |
| 封装： | ROHS COMPLIANT, LQFP-48 |
| 文件页数： | 10/99页 |
| 文件大小： | 1526K |
| 代理商： | WJLXT972MLC.A4-864101 |
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Page 18
Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver
LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
4.0 Signal Descriptions
Table 5
MII Data Interface Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type
Signal Description
A3
B3
C4
A4
60
59
58
57
TXD3
TXD2
TXD1
TXD0
I
Transmit Data.
TXD is a group of parallel data signals that are driven by the MAC.
TXD[3:0] transition synchronously with respect to TX_CLK.
TXD[0] is the least-significant bit.
B4
56
TX_EN
I
Transmit Enable.
The MAC asserts this signal when it drives valid data on TXD.
This signal must be synchronized to TX_CLK.
C5
55
TX_CLK
O
Transmit Clock.
TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
D6
C8
B8
A8
45
46
47
48
RXD3
RXD2
RXD1
RXD0
O
Receive Data.
RXD is a group of parallel signals that transition synchronously with
respect to RX_CLK.
RXD[0] is the least-significant bit.
A7
49
RX_DV
O
Receive Data Valid.
The PHY asserts this signal when it drives valid data on RXD.
This output is synchronous to RX_CLK.
A5
53
RX_ER
O
Receive Error.
Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
B5
54
TX_ER
I
Transmit Error.
Signals a transmit error condition.
This signal must be synchronized to TX_CLK.
B6
52
RX_CLK
O
Receive Clock.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
For details, see Section 5.3.2, Clock Requirements, on page 30 in
the Functional Description section.
B2
62
COL
O
Collision Detected.
The PHY asserts this output when a collision is detected.
This output remains High for the duration of the collision.
This signal is asynchronous and is inactive during full- duplex
operation.
A2
63
CRS
O
Carrier Sense.
During half-duplex operation (register bit 0.8 = 0), the PHY asserts
this output when either transmitting or receiving data packets.
During full-duplex operation (register bit 0.8 = 1), CRS is asserted
only during receive.
CRS assertion is asynchronous with respect to RX_CLK. CRS is
de-asserted on loss of carrier, synchronous to RX_CLK.
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