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参数资料
| 型号： | X4003S8I-4.5A |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封装： | PLASTIC, SOIC-8 |
| 文件页数： | 3/18页 |
| 文件大小： | 378K |
| 代理商： | X4003S8I-4.5A |
X4003/X4005
Characteristics subject to change without notice.
11 of 18
REV 1.1.3 4/30/02
www.xicor.com
CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Note:
(4) This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
Max.
Unit
Test Conditions
COUT
(4)
Output capacitance (SDA, RESET/RESET)
8
pF
VOUT = 0V
CIN
(4)
Input capacitance (SCL, WP)
6
pF
VIN = 0V
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
5V
4.6K
RESET
100pF
SDA
1533
100pF
5V
For VOL = 0.4V
and IOL = 3 mA
RESET
Input pulse levels
0.1VCC to 0.9VCC
Input rise and fall times
10ns
Input and output timing levels
0.5VCC
Output load
Standard output load
A.C. CHARACTERISTICS (Continued)(Over recommended operating conditions, unless otherwise specified)
Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V
(6) Cb = total capacitance of one bus line in pF.
Symbol
Parameter
100kHz
400kHz
Unit
Min.
Max.
Min.
Max.
fSCL
SCL clock frequency
0
100
0
400
kHz
tIN
Pulse width suppression time at inputs
n/a
50
ns
tAA
SCL LOW to SDA data out valid
0.1
0.9
0.1
0.9
s
tBUF
Time the bus free before start of new transmission
4.7
1.3
s
tLOW
Clock LOW time
4.7
1.3
s
tHIGH
Clock HIGH time
4.0
0.6
s
tSU:STA
Start condition setup time
4.7
0.6
s
tHD:STA
Start condition hold time
4.0
0.6
s
tSU:DAT
Data in setup time
250
100
ns
tHD:DAT
Data in hold time
5.0
0
s
tSU:STO
Stop condition setup time
0.6
s
tDH
Data output hold time
50
ns
tR
SDA and SCL rise time
1000
20 +.1Cb(6)
300
ns
tF
SDA and SCL fall time
300
20 +.1Cb(6)
300
ns
tSU:WP
WP setup time
0.4
0.6
s
tHD:WP
WP hold time
0
s
Cb
Capacitive load for each bus line
400
pF
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