参数资料
| 型号： | X40421V14I-CT1 |
| 厂商： | Intersil |
| 文件页数： | 10/25页 |
| 文件大小： | 0K |
| 描述： | IC VOLT MON DUAL SUP/SW 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.6V，2.9V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
X40420, X40421
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the Fault Detection Register is defaulted
to all “0”. The system needs to initialize this register to
all “1” before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a
“1” to a “0” to indicate the failure. At this moment, the
system should perform a read to the register and
noted the cause of the reset. After reading the register
the system should reset the register back to all “1”
again. The state of the Fault Detection Register can be
read at any time by performing a random read at
address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one
byte of data is read by the register read operation.
MRF: Manual Reset Fail Bit (Volatile)
The MRF bit will set to “0” when Manual Reset input
goes active.
WDF: Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when WDO goes active.
LV1F: Low V CC Reset Fail Bit (Volatile)
The LV1F bit will be set to “0” when V CC (V1MON)
falls below V TRIP1 .
LV2F: Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below V TRIP2 .
10
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 8.
Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
May 25, 2006
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| X40426V14I-2.7AT1 | 功能描述:IC SUPERVISR CPU IIC LVS 14TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
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