参数资料
型号: X96010V14IZ
厂商: Intersil
文件页数: 24/26页
文件大小: 0K
描述: IC SENSOR CONDITIONER 14-TSSOP
标准包装: 95
类型: 传感器调节器
输入类型: 电压
输出类型: 电压
接口: 2 线
电流 - 电源: 15mA
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 管件
产品目录页面: 1246 (CN2011-ZH PDF)
7
FN8214.1
October 25, 2005
2-WIRE INTERFACE A.C. CHARACTERISTICS
2-WIRE INTERFACE TEST CONDITIONS
NONVOLATILE WRITE CYCLE TIMING
Notes: 1.
Cb = total capacitance of one bus line (SDA or SCL) in pF.
2.
tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
3.
The minimum frequency requirement applies between a START and a STOP condition.
4.
These parameters are periodically sampled and not 100% tested.
Symbol
Parameter
Min
Typ
Max
Units
Test Conditions / Notes
fSCL
SCL Clock Frequency
1(3)
400
kHz
tIN(4)
Pulse width Suppression Time at
inputs
50
ns
tAA(4)
SCL Low to SDA Data Out Valid
900
ns
tBUF(4)
Time the bus free before start of new
transmission
1300
ns
tLOW
Clock Low Time
1.3
1200(3)
s
tHIGH
Clock High Time
0.6
1200(3)
s
tSU:STA
Start Condition Setup Time
600
ns
tHD:STA
Start Condition Hold Time
600
ns
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
s
tSU:STO
Stop Condition Setup Time
600
ns
tDH
Data Output Hold Time
50
ns
tR(4)
SDA and SCL Rise Time
20
+0.1Cb(1)
300
ns
tF(4)
SDA and SCL Fall Time
20
+0.1Cb(1)
300
ns
tSU:WP(4)
WP Setup Time
600
ns
tHD:WP(4)
WP Hold Time
600
ns
Cb(4)
Capacitive load for each bus line
400
pF
Input Pulse Levels
10 % to 90 % of Vcc
Input Rise and Fall Times, between 10% and 90%
10 ns
Input and Output Timing Threshold Level
1.4V
External Load at pin SDA
2.3k
to Vcc and 100 pF to Vss
Symbol
Parameter
Min
Typ
Max
Units
Test Conditions / Notes
tWC(2)
Nonvolatile Write Cycle Time
5
10
ms
X96010
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