参数资料
型号: XA3SD1800A-4FGG676I
厂商: Xilinx Inc
文件页数: 9/58页
文件大小: 0K
描述: SPARTAN-3ADSP FPGA 1800K 676FBGA
产品培训模块: Extended Spartan 3A FPGA Family
标准包装: 40
系列: Spartan®-3A DSP XA
LAB/CLB数: 4160
逻辑元件/单元数: 37440
RAM 位总计: 1548288
输入/输出数: 519
门数: 1800000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
配用: 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
17
Device DNA Read Endurance
Switching Characteristics
All XA Spartan-3A DSP FPGAs ship in the -4 speed grade. Switching characteristics in this document are designated as
Production, as shown in Table 16.
Production: These specifications are approved once enough production silicon of a particular device family member has
been characterized to provide full correlation between speed files and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes.
Software Version Requirements
Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status.
FPGAs designs using a less mature speed file designation should only be used during system prototyping or pre-production
qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a
production-quality system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE
software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software
updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise
noted, the published parameter values apply to all XA Spartan-3A DSP devices. AC and DC characteristics are specified
using the same numbers for both I-Grade and Q-Grade.
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user guides are updated.
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Timing parameters and their representative values are selected for inclusion below either because they are important as
general design requirements or they indicate fundamental device performance characteristics. The XA Spartan-3A DSP
FPGA speed files (v1.32), part of the Xilinx Development Software, are the original source for many but not all of the values.
The speed grade designations for these files are shown in Table 16. For more complete, more precise, and worst-case data,
use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated
to the simulation netlist.
Table 17 provides the recent history of the XA Spartan-3A DSP FPGA speed files.
Table 15: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
30,000,000
Read
cycles
Table 16: XA Spartan-3A DSP FPGA v1.32 Speed Grade Designations
Device
Production
XA3SD1800A
-4
XA3SD3400A
-4
Table 17: XA Spartan-3A DSP Speed File Version History
Version
ISE Software Release
Description
1.32
ISE 10.1 SP2
Support for Automotive.
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