参数资料
| 型号： | XA3SD3400A-4CSG484I |
| 厂商： | Xilinx Inc |
| 文件页数： | 32/58页 |
| 文件大小： | 0K |
| 描述： | SPARTAN-3ADSP FPGA 3400K 484CSBG |
| 产品培训模块： | Extended Spartan 3A FPGA Family |
| 标准包装： | 84 |
| 系列： | Spartan®-3A DSP XA |
| LAB/CLB数： | 5968 |
| 逻辑元件/单元数： | 53712 |
| RAM 位总计： | 2322432 |
| 输入/输出数： | 309 |
| 门数： | 3400000 |
| 电源电压： | 1.14 V ~ 1.26 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 484-FBGA，CSPBGA |
| 供应商设备封装： | 484-CSPBGA |
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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
38
Clock Buffer/Multiplexer Switching Characteristics
Table 31: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade: -4
Units
Min
Max
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
–1.72
ns
Setup Times
TDS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the distributed RAM
–0.02
–ns
TAS
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
0.36
–ns
TWS
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
0.59
–ns
Hold Times
TDH
Hold time of the BX and BY data inputs after the active transition at the CLK
input of the distributed RAM
0.13
–ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
0.01
–ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
1.01
–ns
Table 32: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade: -4
Units
Min
Max
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on the shift
register output
–4.82
ns
Setup Times
TSRLDS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the shift register
0.18
–ns
Hold Times
TSRLDH
Hold time of the BX or BY data input after the active transition at the CLK input
of the shift register
0.16
–ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
1.01
–ns
Table 33: Clock Distribution Switching Characteristics
Description
Symbol
Minimum
Maximum
Units
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
TGIO
–0.23
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs.
Same as BUFGCE enable CE-input
TGSI
–0.63
ns
Frequency of signals distributed on global buffers (all sides)
FBUFG
0
334
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XA3SD3400A-4FGG676I | 功能描述:SPARTAN-3ADSP FPGA 3400K 676FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-3A DSP XA 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| X-A4A-300L | 制造商:Leach International Corporation 功能描述:MID RANGE - Bulk |
| X-A4C-300M | 制造商:Leach International Corporation 功能描述:MID RANGE - Bulk |
| X-A4M-300L | 制造商:Leach International Corporation 功能描述:MID RANGE - Bulk |
| X-A4M-300M | 制造商:Leach International Corporation 功能描述:MID RANGE - Bulk |
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