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参数资料
| 型号： | XC2C32A-3CP56C |
| 厂商： | XILINX INC |
| 元件分类： | PLD |
| 英文描述： | FLASH PLD, 3 ns, PBGA56 |
| 封装： | 6 X 6 MM, 0.50 MM PITCH, CSP-56 |
| 文件页数： | 9/13页 |
| 文件大小： | 264K |
| 代理商： | XC2C32A-3CP56C |
XC2C32A CoolRunner-II CPLD
DS310 (v1.1) August 30, 2004
Advance Product Specification
1-800-255-7778
R
Schmitt Trigger Input DC Voltage Specifications
AC Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Max.
Units
VCCIO
Input source voltage
1.4
3.9
V
VT+
Input hysteresis threshold voltage
0.5 x VCCIO
0.8 x VCCIO
V
VT-
0.2 x VCCIO
0.5 x VCCIO
V
Symbol
Parameter
-3
-4
-6
Units
Min.
Max.
Min.
Max.
Min.
Max
.
TPD1
Propagation delay single p-term
-
2.8
-
3.8
-
5.5
ns
TPD2
Propagation delay OR array
-
3.0
-
4.0
-
6.0
ns
TSUD
Direct input register clock setup time
1.5
-
1.7
-
2.2
-
ns
TSU1
Setup time fast (single p-term)
1.5
-
1.9
-
2.6
-
ns
TSU2
Setup time (OR array)
1.7
-
2.1
-
3.1
-
ns
THD
Direct input register hold time
0.0
-
0.0
-
0.0
-
ns
TH
P-term hold time
0.0
-
0.0
-
0.0
-
ns
TCO
Clock to output
-
2.8
-
3.7
-
4.7
ns
FTOGGLE(1)
Internal toggle rate
-
500
-
450
-
300
MHz
FSYSTEM1(2) Maximum system frequency
-
417
-
323
-
200
MHz
FSYSTEM2(2) Maximum system frequency
-
385
-
303
-
182
MHz
FEXT1(3)
Maximum external frequency
-
233
-
179
-
137
MHz
FEXT2(3)
Maximum external frequency
-
222
-
172
-
128
MHz
TPSUD
Direct input register p-term clock setup time
0.6
-
0.4
-
0.9
-
ns
TPSU1
P-term clock setup time (single p-term)
0.6
-
0.6
-
1.3
-
ns
TPSU2
P-term clock setup time (OR array)
0.8
-
0.8
-
1.8
-
ns
TPHD
Direct input register p-term clock hold time
0.9
-
1.5
-
1.6
-
ns
TPH
P-term clock hold
0.9
-
1.3
-
1.2
-
ns
TPCO
P-term clock to output
-
3.7
-
5.0
-
6.0
ns
TOE/TOD
Global OE to output enable/disable
-
4.0
-
4.2
-
5.5
ns
TPOE/TPOD
P-term OE to output enable/disable
-
5.3
-
5.5
-
6.7
ns
TMOE/TMOD
Macrocell driven OE to output enable/disable
-
4.8
-
5.0
-
6.9
ns
TPAO
P-term set/reset to output valid
-
4.9
-
5.5
-
6.8
ns
TAO
Global set/reset to output valid
-
4.0
-
4.5
-
5.5
ns
TSUEC
Register clock enable setup time
1.8
-
2.0
-
3.0
-
ns
THEC
Register clock enable hold time
0.0
-
0.0
-
0.0
-
ns
TCW
Global clock pulse width High or Low
0.9
-
1.4
-
2.2
-
ns
TPCW
P-term pulse width High or Low
3.0
-
4.0
-
6.0
-
ns
TCONFIG(4)
Configuration time
-
50
-
50
-
50
s
Notes:
1.
FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet).
2.
FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per
macrocell while FSYSTEM2 is through the OR array.
3.
FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4.
Typical configuration current during TCONFIG is 500 A.
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