参数资料
| 型号： | XC2S100E-6FTG256C |
| 厂商： | Xilinx Inc |
| 文件页数： | 38/108页 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-IIE FPGA 100K 256FBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 90 |
| 系列： | Spartan®-IIE |
| LAB/CLB数： | 600 |
| 逻辑元件/单元数： | 2700 |
| RAM 位总计： | 40960 |
| 输入/输出数： | 182 |
| 门数： | 100000 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-FTBGA |
| 其它名称： | 122-1322 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页
DS077-3 (v3.0) August 9, 2013
35
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)
Symbol
Description
Speed Grade
Units
All
-7
-6
Min
Max
TICKOFDLL
LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with DLL.
1.0
3.1
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
3.
DLL output jitter is already included in the timing calculation.
4.
For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Symbol
Description
Device
Speed Grade
Units
All
-7
-6
Min
Max
TICKOF
LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
XC2S50E
1.5
4.4
4.6
ns
XC2S100E
1.5
4.4
4.6
ns
XC2S150E
1.5
4.5
4.7
ns
XC2S200E
1.5
4.5
4.7
ns
XC2S300E
1.5
4.5
4.7
ns
XC2S400E
1.5
4.6
4.8
ns
XC2S600E
1.6
4.7
4.9
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
3.
For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
相关PDF资料 |
PDF描述 |
|---|---|
| ACB91DHFT-S621 | EDGECARD 182POS SMD W/O POST |
| ABB91DHFT-S621 | EDGECARD 182PS .050 SMD W/O POST |
| ACB91DHFT-S578 | EDGECARD 182POS .050 SMD W/POSTS |
| XC2S100E-6FT256C | IC FPGA 1.8V 600 CLB'S 256-FBGA |
| ABB91DHFT-S578 | EDGECARD 182POS .050 SMD W/POSTS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2S100E-6FTG256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E-6PQ208C | 功能描述:IC FPGA 1.8V 600 CLB'S 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-IIE 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
| XC2S100E-6PQ208I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E-6PQG208C | 功能描述:IC FPGA 1.8V 600 CLB'S 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-IIE 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
| XC2S100E-6PQG208I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
发布紧急采购，3分钟左右您将得到回复。