参数资料
| 型号： | XC3030L-8VQ64C |
| 厂商： | Xilinx Inc |
| 文件页数： | 67/76页 |
| 文件大小： | 0K |
| 描述： | IC FPGA C-TEMP 3.3V 64-VQFP |
| 产品变化通告： | XC3000(L) Discontinuation 01/Feb/2003 |
| 标准包装： | 64 |
| 系列： | XC3000A/L |
| LAB/CLB数： | 100 |
| RAM 位总计： | 22176 |
| 输入/输出数： | 54 |
| 门数： | 2000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 64-TQFP |
| 供应商设备封装： | 64-VQFP（10x10） |
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R
November 9, 1998 (Version 3.1)
7-9
XC3000 Series Field Programmable Gate Arrays
7
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. For
example, the XC3020A has 64 such blocks arranged in 8
rows and 8 columns. The development system is used to
compile the configuration data which is to be loaded into
the internal configuration memory to define the operation
and interconnection of each block. User definition of CLBs
and their interconnecting networks may be done by auto-
matic translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the asyn-
chronous RD which, when enabled and High, is dominant
over clocked inputs. All flip-flops are reset by the
active-Low chip input, RESET, or during the configuration
process. The flip-flops share the enable clock (EC) which,
when Low, recirculates the flip-flops’ present states and
inhibits response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control inputs
and select their sources. The user may also select the
clock net input (K), as well as its active sense within each
CLB. This programmable inversion eliminates the need to
route both phases of a clock signal throughout the device.
Q
COMBINATORIAL
FUNCTION
LOGIC
VARIABLES
D
RD
G
F
DIN
F
G
QX
QY
DIN
F
G
QY
QX
F
Q
D
RD
ENABLE CLOCK
CLOCK
DIRECT
RESET
1 (ENABLE)
A
B
C
D
E
DI
EC
K
RD
Y
X
X3032
0 (INHIBIT)
(GLOBAL RESET)
CLB OUTPUTS
DATA IN
0
1
0
1
MUX
Figure 5: Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of
function. It has the following:
-
five logic variable inputs A, B, C, D, and E
-
a direct data in DI
-
an enable clock EC
-
a clock (invertible) K
-
an asynchronous direct RESET RD
-
two outputs X and Y
Product Obsolete or Under Obsolescence
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC3030L-8VQ64I | 功能描述:IC FPGA I-TEMP 3.3V 64-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC3000A/L 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC3042 | 制造商:Xilinx 功能描述: |
| XC3042-100CB100B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| XC3042-100CB100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| XC3042-100CB100M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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