参数资料
型号: XC3190A-3PC84C
厂商: Xilinx Inc
文件页数: 22/76页
文件大小: 0K
描述: IC LOGIC CL ARRAY 9000GAT 84PLCC
产品变化通告: XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
标准包装: 1
系列: XC3000A/L
LAB/CLB数: 320
RAM 位总计: 64160
输入/输出数: 70
门数: 6000
电源电压: 4.25 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC
产品目录页面: 601 (CN2011-ZH PDF)
其它名称: 122-1046
R
November 9, 1998 (Version 3.1)
7-31
XC3000 Series Field Programmable Gate Arrays
7
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
D/P
RESET
X5993
FPGA
General-
Purpose
User I/O
Pins
+5 V
M0
M1
PWRDWN
CCLK
DIN
STRB
D0
D1
D2
D3
D4
D5
D6
D7
RESET
I/O
Port
Micro
Computer
DOUT
HDC
LDC
M2
...
Other
I/O Pins
INIT
+5 V
5 k
If Readback is
Activated, a
5-k
Resistor is
Required in
Series with M1
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
*
Figure 29: Slave Serial Mode Circuit Diagram
Product Obsolete or Under Obsolescence
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