参数资料
型号: XC4008E-4PG191I
厂商: Xilinx Inc
文件页数: 4/68页
文件大小: 0K
描述: IC FPGA I-TEMP 5V 4SPD 191-CPGA
产品变化通告: XC4000(E,L) Discontinuation 01/April/2002
标准包装: 12
系列: XC4000E/X
LAB/CLB数: 324
逻辑元件/单元数: 770
RAM 位总计: 10368
输入/输出数: 144
门数: 8000
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 191-BCBGA
供应商设备封装: 191-CPGA(47.25x47.25)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-16
May 14, 1999 (Version 1.6)
Figure 8 shows the write timing for level-sensitive, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Figure 9 and Figure 10 show block diagrams of a CLB con-
gured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Conguration
Both RAM and ROM implementations of the XC4000
Series devices are initialized during conguration. The ini-
tial contents are dened via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not dened, all RAM contents
are initialized to all zeros, by default.
RAM initialization occurs only during conguration. The
RAM content is not affected by Global Set/Reset.
Table 7: Single-Port Level-Sensitive RAM Signals
G'
G1 G4
F1 F4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6748
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WRITE PULSE
MUX
4
C1 C4
4
WE
D1
D0
EC
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
RAM Signal
CLB Pin
Function
D
D0 or D1
Data In
A[3:0]
F1-F4 or G1-G4
Address
WE
Write Enable
O
F’ or G’
Data Out
WC
T
ADDRESS
WRITE ENABLE
DATA IN
AS
T
WP
T
DS
T
DH
T
REQUIRED
AH
T
X6462
Figure 8: Level-Sensitive RAM Write Timing
Product Obsolete or Under Obsolescence
相关PDF资料
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XC4008E-4PG191C IC FPGA C-TEMP 5V 4SPD 191-CPGA
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